A semiconductor integrated circuit typically includes metallized interconnection electrodes in a pattern which overlies regions of both relatively thick and thin insulating layers. Typically a thick insulating layer region comprises a relatively thick layer of silicon dioxide, called "field oxide," located on a major planar surface of the silicon body in which the circuit is integrated; whereas a thin insulating layer region typically comprises a relatively thin silicon dioxide layer, called "gate oxide," located on the same major planar surface of the silicon body in regions complementary to the thick insulating layer regions (field oxide regions). Insulated gate field effect transistors are located in these regions of gate oxide. At the boundary between the thick and thin insulating regions a step is formed having an oxide sidewall surface (stemming from the field oxide) over which the metallized interconnection electrode must go.
A typical such situation, somewhat simplified for purposes of clarity only, is illustrated in FIG. 1. (The broken lines 4--4 and 5--5 are useful in defining typical cross sections.) Here a top view in perspective shows a monocrystalline silicon body 10; a thin central gate oxide layer 11; a thick oxide layer having a left-hand field oxide portion 12 and a right-hand field oxide portion 13; a first step 14 located at the boundary of the left-hand field oxide portion 13 with the gate oxide layer 11; a second step 15 located at the boundary of the gate oxide 11 with the right-hand portion 13; a first electrode 17 running along a path extending from the left-hand field oxide portion 12 to a termination at a point overlying the central gate oxide layer 11; and a second electrode 16 running along a path extending from the left-hand field oxide 12 to the right-hand field oxide 15. Thus the first electrode 16 crosses over both steps 14 and 15, whereas the second electrode 17 crosses over only the first step 14, for illustrative purposes only. For illustrative purposes, the first electrode 16 can be a gate electrode metallization which interconnects in two directions, and the second electrode 17 can be a gate electrode which interconnects in but one direction.
When these electrodes 16 and 17 are fabricated by conventional deposition of metal silicide on polycrystalline silicon followed by selective masking and etching, there is an undesirable tendency for the electrodes 16 and 17 to be joined (shorted) together by a residual metal strip running along the bottom of the sidewall of the step, because of the tendency of the etching not te remove completely some portions of the electrodes at the step. It would therefore be desirable to have a method for fabricating interconnection which avoids this problem.